Personal Professional Overview:
Edward Olson, Senior GPS/RF Design Engineer
- Over seventeen years of experience in "whole-product" hardware design and management, from product concepting and specification to design and volume manufacturing
- Proven senior level project management, design and engineering skills
- Thorough understanding of GPS tracking, satellite communications, R&D and broad-based knowledge of RF/RFIC/analog/digital technology and industry trends
Focused on GPS integration into products designed for a wide variety of consumer, commercial and military applications. Attention to product concept development, project planning, team leadership, multi-task coordination, critical path, workmanship and budget as they are all vital to a competitive product entry into market.
Technical RF lead for Hammerhead--flagship product & industry's first single-die receiver IC. Responsible for system specifications, collaboration with Infineon design team, design validation. Targeted for mobile handset applications.
Silicon Valley-San Jose, California
Developed leading-edge A-GPS chips for use in mobile phones (e.g. Sharp 904sh), PDAs (e.g. HP iPaq mobile messenger). Achieved receiver sensitivity down to -160dBm, suitable for deep-indoor positioning. Design validation and production test development for LN-22, Global Locate's previous generation RF front-end IC.
RFIC design in 90nm CMOS, constant-gain bias sources, 5th-order Butterworth filter. Simulation using Cadence Virtuoso ADE & Spectre. Taped out successful test chip and RF macro for integration with baseband processor into single-chip receiver.
System design, including frequency plan design, Gain/Noise Figure analysis, Matlab simulation of MASH sigma-delta PLL & Phase-Noise Integration.
Supported customer application of chipsets through design trade-off analysis, interference prevention & mitigation, schematics, PCB layout & performance verification.
Related White Papers: Effects of Reference Clock Phase Noise on SNR; Impact of Reference Clock AFC on SNR, Data Decoding & Doppler Frequency Estimation
Consulting project details: Reviewed and qualified circuit board layouts for Smartphone reference design. Advised on antenna selection. Provided frequency plan and system analysis. Review and optimization of schematic.
Fabless Semiconductor Company
Silicon Valley-Redwood City, California
Mainstay Venture Management
Consulting project details: Provided strawman design and cost analysis for a proprietary GPS handheld consumer product. Work included technical concept development, design of multi-band receiver, antenna diversity, communication link, power supply, GUI. Managed domestic and offshore manufacturing cost estimates.
Crested Butte, Colorado
Consulting project details: Review of PCB layouts, interference analysis and mitigation, ongoing performance and yield improvement. Technical liaison with Enfora/Plano, Texas, USA and Sarantel/Wellingborough, United Kingdom.
SkyGolf, Handheld Golf GPS Systems
Consulting project details: GPS integration into a PC card, developed serial interface in FPGA. Design/debug of Ethernet PC card.
Mobile Connectivity Products
Silicon Valley-Newark, California
Managed development of core technology and flagship products:
Santa Clara, California
Single- and dual-frequency precision GPS receivers,
Integration of GPS, WAAS and radio beacon receivers on one circuit board,
750Kgate, leading-edge GPS correlator ASIC.
Interfaced with Marketing department to construct requirements and specifications documents. Evaluated RF and system architectures and implementation. Managed development schedule, budget and
Defined and supervised verification tests and production test strategies. Organized and chaired ISO 9001 design reviews and led the ECO process to introduce products into full-scale manufacturing. Supervised design budgets of over $5M.
Designed industry's smallest and first sub-$100 OEM GPS Module for in-car Navigation (Hertz Neverlost), asset tracking and handheld applications. Coordinated implementation of high-volume (40kpcs/mo) manufacturing in Osaka, Japan. Included high stability discrete XO, innovative temperature compensation. System architecture and frequency plan design for GPS+GLONASS receiver. Numerous PLLs, GaAS, and bipolar LNA blocks, filters, impedance matching, noise matching, Wilkinson splitter, diplexer, FCC and
CE marking and RFIC debug.
Extensive experience remote-managing developments by the corporation's engineering team in Moscow, Russia, and international collaboration with French engineering department.
Completed special projects such as: design of a dual-band LNA
(2 dB NF) including microstrip diplexer, dual-band receiver frequency plan design, and developed specifications for TCXO performance under vibration. Consulted on numerous developments and integrations for LNA, PLL and oscillator issues, vibration-induced phase noise problems and EMI/RFI issues.
Participated in Strategic Business Planning process. Collaborated on product roadmap, marketing requirements document (MRD), product launch scheduling. Published white paper on relationships between NF, gain and system performance in 2001.
GPS receivers in a type II PCMCIA format; principal designer responsible for digital and RF design; project definition through product release; strict space/power constraints, dual down-conversion, IF/BB filter design, Motorola 68330 embedded controller, crystal oscillator, FFC and CE marking, design-failure-mode effect analysis (DFMEA), manufacturing issues, project management responsibilities. Designed PCMCIA serial comm interface in FPGA.
Silicon Valley-Sunnyvale, California
Cadence Design Systems, Diablo Research Corporation
Engineering consultant with emphasis on design for high-volume, low-cost manufacture. Responsibilities included the design, prototype, test of consumer products.
Silicon Valley,-Sunnyvale, California
Electronic Price Tag System: a 900 MHz spread-spectrum packet radio transceiver, and a PC/AT-bus card with embedded controller and Xilinx FPGA to implement redundant communication link.
High efficiency DC-DC converters, requiring wide input range, adjustable output voltage, and high battery utilization.
RF-induction lightbulb, designed and implemented an automated test facility to measure and record lumen output and efficiency, power-factor-corrected switching power supplies; extensive PSpice simulation and Monte Carlo analysis; MTBF analysis; FCC/UL; R&D with Peltier (thermoelectric) modules. Designed an RFI screen room.